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HomeNewsIISC creates design framework to build next-generation analog computing chipset

IISC creates design framework to build next-generation analog computing chipset

The chipsets are expected to be faster and require less power than the digital chips used in most electronic devices.

A team of researchers at the Indian Institute of Science (IISc) has created a design framework to build next-generation analog computing chipsets. These chipsets are expected to be faster and require less power than the digital chips used in most electronic devices.   

The team has developed a prototype of an analog chipset, ARYABHAT-1 (Analog Reconfigurable technologY And Bias-scalable Hardware for AI Tasks), using a new design framework. 

Such chipsets can be very helpful for artificial intelligence-based applications like object and speech recognition devices or those that require massive parallel computing operations at high speeds. The chipset can provide orders of magnitude of improvement in power and size. In applications not requiring precise calculations, analog computing has the potential to outperform digital computing, as the former is more energy-efficient.  

Read More: IISc Researchers Build An ML Algorithm To Discover Human Brain Connectivity

However, there are technological hurdles. Unlike digital chips, the testing and co-design of analog processors are comparatively complex. They must be customized individually when transitioning to a new application or the next generation of technology. Also, their designs are expensive. 

To overcome such challenges, the team has designed this new framework that enables the development of analog processors that scale like digital processors. Their chipset can be programmed and reconfigured to port the same analog modules across different applications and generations of process design.

Also, different machine learning architectures can be programmed on ARYABHAT. Similar to digital processors, it can operate robustly across a wide range of temperatures. According to researchers,  the architecture is bias-scalable, i.e., its performance remains the same even when the operating conditions like current and voltage are changed. 

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Sahil Pawar
Sahil Pawar
I am a graduate with a bachelor's degree in statistics, mathematics, and physics. I have been working as a content writer for almost 3 years and have written for a plethora of domains. Besides, I have a vested interest in fashion and music.

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