Researchers at the Automation, Verification and Security (AVS) Lab at the Indian Institute of Technology (IIT) Guwahati, develops secure and dependable integrated circuits (ICs) for faster and efficient computing.
The research looks at all aspects of the automated electronics design process like synthesis, verification and security, and contributes towards strengthening the electronics manufacturing ecosystem in our country.
The findings have been published in top tier journals and conferences of IEEE. The research team is funded by ECR, CRG and Interdisciplinary Cyber-Physical Systems (ICPS) grants from the Department of Science & Technology, Govt. of India and by a Research Fellowship from Intel (India).
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With the Government of India’s recent approval of the Rs 76,000-crore scheme to boost semiconductor manufacturing in the country, efficient EDA aids such as those designed by the IIT Guwahati team will support and promote self-sufficiency in chip design.
The paper has been authored by Dr. Chandan Karfa, Associate Professor, Department of Computer Science & Engineering, IIT Guwahati and co-authored his research students Mr Mohammed Abderehman, Mr. Debebdara Senapati, Mr Surajit Das, Ms Priyanka Panigrahi and Ms Nilotpola Sarma.
Some alumni who contributed to these endeavors are Ramanuj Chouksey, Jay Oza, Yom Nigam, Abdul Khader, and Jayprakash Patidar. The team has collaborated with various international experts. Dr. Chandan Karfa is also the recipient of the Qualcomm Faculty Award 2021.
IIT Guwahati team emphasize on hardware acceleration specifications that are often written in high-level languages like in C/C++ and are converted to hardware code (or register transfer level or Register−Transfer Level (RTL code), in a process called High-Level Synthesis (HLS).
Due to the complex conversation process, HLS translation may introduce bugs in the design and therefore stringent validation steps are required. The RTL simulators are used to validate HLS, but these are slow and complex.
Dr. Chandan Kafa, said, “A promising technology to improve computational efficiency is hardware accelerators. In hardware acceleration, specific tasks can be offloaded to dedicated hardware instead of being performed by the CPU core of the system. For example, visualization processes may be offloaded onto a graphics card, thereby freeing the CPU to perform other tasks.”
He further added that they have developed two tools to validate the HLS process. One is FastSim, an RTL simulator that is 300 times faster than existing commercial simulators. and the other is DEEQ, which is an automated C to RTL equivalence checking tool for HLS verification.
